CMOS image sensors (Complementary Metal Oxide Semiconductor) and CCD sensors (Charge Coupled Device) are used in endoscopes, digital cameras, scanners and other electronic devices. Since they have an amplifier for each unit cell, CMOS image sensors can produce signals with a higher S/N ratio compared with CCD sensors. They also have the advantage that the power consumption can be controlled by using a CMOS logic device manufacturing process.
In regard to CMOS image sensors of this type, Japanese Kokai Patent Publication No. 2006-217410 discloses a solid-state imaging device with a wide dynamic range that includes an overflow gate that transfers overflow photoelectric charge from a photodiode to an accumulating capacitance element during an accumulation operation. This maintains both high sensitivity and a high S/N ratio.
FIG. 12 illustrates the construction of one pixel of a conventional CMOS image sensor and a column output circuit that outputs a signal read from the one pixel. Pixel Pj includes a photodiode PD for photoelectric conversion, a transfer transistor (transfer gate) M1 connected to photodiode PD, a reset transistor M2 connected to transfer transistor M1, a source follower transistor M3, the gate of which is connected to node N1 that connects transfer transistor M1 and reset transistor M2 and a row (line) selection transistor M4 connected between source follower transistor M3 and column (rank) signal line CLj (vertical signal line). Pixel Pj comprises four transistors M1, M2, M3 and M4 which are N-channel enhancement mode MOS transistors.
Transistors M1, M2, M3 and M4 are off during the light exposure period or charge accumulation period of photodiode PD. After completion of the charge accumulation period, gate signal Xj of transistor M4 goes high, pixel Pj is selected to begin reading pixel Pj. FIG. 12 illustrates only one pixel Pj, but all the pixels on one line in the array are selected when gate signal Xj goes high.
When the read period starts, gate signal R of reset transistor M2 goes high. The capacitance of parasitic capacitance CFD at a floating diffusion (FD) at node N1 is reset to Vdd. After reset transistor M2 is turned off, gate signal TX of transfer transistor M1 goes high to transfer all the charge accumulated in photodiode PD to FD. The transferred charge supplied the input to the gate of source follower transistor M3. Transistors M3 and M4 produce an amplified input voltage at node N2 of column signal line CLj.
A column signal line is connected to each of the pixels in each column of the array. A constant current source I is also connected between node N2 and ground of the column signal line. Sample-and-hold signal SH causes sample-and-hold transistor M5 to accumulate the signal of pixel Pj at node N2 of column signal line CLj in capacitor C. This accumulated signal is read when gate signal ΦCol of column output transistor M6 goes high. In this way, signals for one line's worth of pixels are read via the column signal line from multiple pixels arranged two-dimensionally, and the signals for one line's worth of pixels will be output in sequence to each pixel.
In order to improve the sensitivity of the CMOS image sensor, the S/N ratio of the signals read from pixels must be improved. The charge accumulated in photodiode PD can be considered as being amplified by a multistage amplifier circuit and output. FIG. 13 represents this multistage amplifier circuit schematically. Equation (1) gives the noise factor F in such a multistage amplifier circuit.
                    F        =                              F            1                    +                                                    F                2                            -              1                                      G              1                                +                                                    F                3                            -              1                                                      G                1                            ⁢                              G                2                                              +                                                    F                4                            -              1                                                      G                1                            ⁢                              G                2                            ⁢                              G                3                                              +          …                                    (        1        )            If the value of F approaches 1, the noise rejection performance will improve.
As is evident from equation (1), the S/N ratio may be improved by raising the gain of the initial stage. For this purpose, capacitance CFD of FD of a pixel may be made smaller, and signal voltage VF (VFD=Q/CFD) of the charge accumulated in FD may be made larger. However, when capacitance CFD of FD is made smaller, capacitance CPD of photodiode PD must also be made correspondingly smaller. This is because all the charge accumulated in photodiode PD must be transferred to FD. The maximum amplitude of photodiode PD is about 1 V. When capacitance CPD of photodiode PD becomes smaller, the amount of charge accumulated in photodiode PD corresponding to the number of electrons decreases.
External light includes so-called shot noise. When the number of electrons accumulated in photodiode PD drops below a certain constant value, the S/N ratio falls. The S/N ratio of photodiode PD can be represented by the equation (2).
                              S          N                =                  20          ⁢                                          ⁢                      log            ⁡                          (                                                Signal                  ⁡                                      (                    N                    )                                                                                        Signal                    ⁡                                          (                      N                      )                                                                                  )                                                          (        2        )            where: N is the number of accumulated electrons. To suppress the effects caused by shot noise, the S/N ratio should be 40 dB or more.
Thus with a conventional CMOS image sensor, when capacitance CFD of FD is made smaller with the intention of improving the S/N ratio (gain) to improve sensitivity, the number of electrons accumulated in photodiode PD decreases, and conversely, there is the incompatible problem of the S/N ratio dropping. The present invention solves this trade-off problem by improving the S/N ratio and providing a high-sensitivity imaging device.